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翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク Low Power Flip-Flop Techniques ： ウィキペディア英語版 Low Power Flip-Flop Techniques Low Power flip-flops are becoming important for implementing low power devices. They are essentially Flip-flop (electronics) but with additional features that ensure low power consumption of the flip flop. ==Motivation== In most VLSI devices , maximum power dissipation is due to the clock network and clocked sequential elements. It can account to anywhere between 25% - 40% of the total power according to the variation of parameters like clock frequency, deeper pipelining etc in a design. Sequential elements , latches and flip flops dissipate power when there is switching in their internal capacitance. This may happen with every clock transition/pulse into the sequential element. Sometimes the sequential elements need to change their state , but sometimes they retain their state and their output remains the same , before and after the clock pulse. This leads to unnecessary dissipation of power due to clock transition. If flip flops are designed in such a way that they are able to gate the clock with respective to their own internal data path, only to use the clock when needed , power dissipation can be brought down.〔 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Low Power Flip-Flop Techniques」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.